This invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device comprising plural semiconductor chips laminated in a resin sealing body and a method of manufacturing the same.
One method of increasing the capacity of memory circuits is known wherein two semiconductor chips housing memory circuits are laminated together, and the two semiconductor chips are sealed in a resin sealing body to form a stacked type semiconductor device. Various structures have been proposed for this stacked type semiconductor device, and marketed. For example, in Japanese Published Unexamined Patent Publication No. Hei 7(1995)-58281, an LOC (Lead On Chip) stacked type semiconductor device is disclosed. In Japanese Published Unexamined Patent Publication No. Hei 4(1992)-302165, a tub structured stacked type semiconductor device is disclosed.
A LOC stacked type semiconductor device has a structure essentially comprising a first semiconductor chip and a second semiconductor chip wherein plural electrodes are formed on a circuit-forming surface which is the front surface (a main surface) of a front and rear surface (a main surface and another main surface opposite each other), plural first leads adhesion-fixed to the circuit-forming surface of the first semiconductor chip with the interposition of an insulating film and electrically connected to the electrodes of this circuit-forming surface via bonding wires, plural second leads adhesion-fixed to the circuit-forming surface of the second semiconductor chip with the interposition of an insulating film and electrically connected to the electrode of this circuit-forming surface via bonding wires, and a resin sealing body which seals the first semiconductor chip, second semiconductor chip, inner parts of the first leads, inner parts of the second leads and bonding wires. The first semiconductor chip and second semiconductor chip are laminated with their circuit-forming surfaces facing each other. The first leads and second leads are joined with their connecting parts mutually superimposed.
A tub structured stacked type semiconductor device comprises a first semiconductor chip fixed to the front surface (a main surface) of a front and rear surface (a main surface and another main surface opposite each other) of a tub (known also as a die pad) via an adhesive layer, a second semiconductor chip fixed to the rear surface of the tub (other main surface) via an adhesive layer, plural exclusive leads electrically connected to electrodes of one of the first semiconductor chip and second semiconductor chip via bonding wires, plural common leads electrically connected to the electrodes of the first semiconductor chip and second semiconductor chip via bonding wires, and a resin sealing body which seals the first semiconductor chip, second semiconductor chip, inner parts of the exclusive leads, inner parts of the common leads and the bonding wires. The electrodes of the first semiconductor chip and second semiconductor chip are arranged in rows along the opposite long sides of the circuit-forming surface. The exclusive leads and common leads are respectively disposed outside the two long sides of the semiconductor chip.
The inventors, as a result of examining the aforesaid stacked type semiconductor devices, identified the following problems.
(1) In LOC stacked type semiconductor devices, the first leads which are electrically connected to the electrodes of the first semiconductor chip via bonding wires and the second leads which are electrically connected to the electrodes of the second semiconductor chip via bonding wires, are joined to each other partially superimposed. In the case of such a construction, the device must be manufactured using two lead frames, so manufacturing costs increased.
(2) In LOC stacked type semiconductor devices, after electrically connecting the electrodes and leads of the semiconductor chips via bonding wires, the two semiconductor chips are laminated by superimposing the two lead frames. In this case, the bonding wires easily tend to deform when the semiconductor chips are laminated, and this led to a decrease of yield.
(3) In tub structured stacked type semiconductor devices, the semiconductor chips are mounted on the front and rear surfaces of the tub. In such a construction, as it is difficult to bring the tub into contact with a heat stage after mounting the semiconductor chips on the front and rear surfaces of the tub, it is difficult to heat the semiconductor chip to the temperature required for wire bonding. Therefore, bad contacts easily occur between the electrodes of the semiconductor chip and bonding wires, and this leads to a decrease of yield.
(4) In a tub structured type semiconductor device, the lead frames must be inverted after electrically connecting the electrodes of the semiconductor chip mounted on the front surface of the tub with the leads, and before electrically connecting the electrodes of the semiiconductor chip mounted on the rear surface of the tub with the leads. This leads to a decrease of productivity.
The bonding wires also easily deform when the lead frames are inverted, and this led to a decrease of yield.
It is therefore an object of this invention to provide a technique for manufacturing a semiconductor device wherein plural semiconductor chips are laminated and these plural semiconductor chips are sealed in a resin sealing body, which permits cost reduction.
It is another object of this invention to provide a technique for manufacturing a semiconductor device wherein plural semiconductor chips are laminated and these plural semiconductor chips are sealed in aresin sealing body, which achieves higher yield.
It is another object of this invention to provide a technique for manufacturing the a semiconductor device wherein plural semiconductor chips are laminated and these plural semiconductor chips are sealed in a resin sealing body, which achieves higher production.
These and other objects and features of this invention will become apparent from the following description and drawings appended thereto.
The representative features of the Invention described in this Application may be simply summarized as follows.
(1) A semiconductor device comprising:
a resin sealing body,
plural semiconductor chips situated inside the resin sealing body and formed of rectangular-shaped plane surfaces, having a first main surface and second main surface facing each other, and having electrodes disposed on the first side of a first side and a second side of the first main surface, the first side and second side facing each other, and
leads having inner parts situated inside the resin sealing body and outer parts situated outside the resin sealing body, the leads being electrically connected to electrodes of the plural semiconductor chips via bonding wires, wherein:
the respective first main surfaces of the plural semiconductor chips are aligned in the same direction such that their respective first sides are situated on the same side, and the plural semiconductor chips are laminated in positions offset with respect to one another such that the electrodes of one of the mutually opposite semiconductor chips are situated further outside than the first side of the other semiconductor chip.
(2) A semiconductor device as defined in the aforesaid (1), wherein:
the plural semiconductor chips are laminated in positions offset with respect to one another such that the second side of one of the mutually opposite semiconductor chips is situated further inside than the second side of the other semiconductor chip.
(3) A semiconductor device comprising:
a resin sealing body having a rectangular plane surface,
first and second semiconductor chips situated inside the resin sealing body and formed of rectangular-shaped plane surfaces, having a first main surface and second main surface facing each other, and having electrodes disposed on the first side of a first side and a second side of the first main surface, the first side and second side facing each other,
first leads having inner parts situated inside the resin sealing body, and outer parts projecting from the first side of the mutually opposite first side and second side of the resin sealing body situated outside the resin sealing body, the inner parts being electrically connected to the electrodes of the first semiconductor chip via bonding wires, and
second leads having inner parts situated inside the resin sealing body, and outer parts projecting from the second side of the resin sealing body situated outside the resin sealing body, the inner parts being electrically connected to the electrodes of the second semiconductor chip via bonding wires,
wherein:
the second main surface of the first semiconductor chip and the first main surface of the second semiconductor chip are aligned facing each other with their respective first sides situated on the side of the second leads, and the first and second semiconductor chips are laminated in positions offset with respect to one another such that the electrodes of the second semiconductor chip are situated further outside than the first side of the first semiconductor chip, and the second side of the first semiconductor chip is situated further outside than the second side of the second semiconductor chip, and
the inner parts of the first leads are adhesion-fixed to the first main surface of the first semiconductor chip.
(4) A semiconductor device as defined in the aforesaid (3), wherein:
the ends of the inner parts of the first leads are disposed in the vicinity of the electrodes of the first semiconductor chip.
(5) A method of manufacturing a semiconductor device comprising a first and second semiconductor chip formed of rectangular-shaped plane surfaces and having a mutually opposite first main surface and second main surface, comprising the steps of:
preparing the first and second semiconductor chip in which electrodes are disposed on one side of a first side and a second side of the first main surface, the sides facing each other, and preparing a lead frame comprising first leads and second leads having inner parts and outer parts, the ends of these inner parts facing each other,
adhesion-fixing the first semiconductor chip to the inner parts of the first leads with the first main surface of the first semiconductor chip and inner parts of the leads facing each other such that the first side of the first semiconductor chip is situated on the side of the second leads,
aligning the second main surface of the first semiconductor chip and first main surface of the second semiconductor chip such that the first side of the second semiconductor chip is situated on the side of the second leads, and adhesion-fixing the first semiconductor chip and second semiconductor chip in positions offset with respect to one another such that the electrodes of the second semiconductor chip are situated further outside than the first side of the first semiconductor chip, and
electrically connecting the electrodes of the first semiconductor chip to the inner parts of the first leads via bonding wires, and electrically connecting the electrodes of the second semiconductor chip to the inner parts of the second leads via bonding wires.